Technical Write-Up: CM2 SPD Driver 1. Overview The CM2 SPD Driver is a dual-channel, high-speed interface driver designed specifically for Serial Presence Detect (SPD) hubs and memory module controllers compliant with the JEDEC DDR4/5 standards (particularly governing the CM2 form factor or chipset). It acts as the physical layer bridge between the I3C/I²C host controller and the SPD EEPROM or hub device on a DDR5 memory module (RDIMM, LRDIMM, or SODIMM). This driver enables robust, low-latency communication for critical functions including:
Module configuration and temperature monitoring. Manufacturing data access (PPI, serial number). Dynamic voltage and frequency scaling (DVFS) handshake. Sideband bus arbitration for multi-module systems.
2. Key Features
Protocol Support: I²C (up to 1 MHz) and I3C Basic (up to 12.5 MHz). Supply Voltage: 1.0V – 1.2V core; 1.8V I/O (optional 3.3V tolerance). Drive Strength: Programmable 2/4/8/12 mA slew-rate controlled output. SPD Hub Compatibility: Direct interface with JEDEC SPD5118, TSE2004, and SE97B thermal sensors. Bus Capacitance Compensation: Up to 250 pF load per channel. Fault Protection: Under-voltage lockout (UVLO), thermal shutdown, and SDA/SCL bus contention detection. Low-Power Modes: Idle (≤5 µA) and suspend (≤0.5 µA) with wake-on-activity. cm2 spd driver
3. Functional Description 3.1 Block Architecture The CM2 SPD driver consists of two independent bidirectional channels: Channel A (SPD Main) and Channel B (SPD Redundant) . Each channel comprises:
Input hysteresis comparator: For noise rejection on SDA/SCL. Open-drain output stage: With adjustable fall-time control. Active pull-up bypass: Allows external 1kΩ resistors or internal 50 µA current sources. Clock stretching arbiter: Prevents I²C deadlock due to slow slave responses. Bus monitor logic: Detects start/stop conditions and idle bus timeout.
3.2 Protocol Handling
I²C Mode: Standard (100 kHz) / Fast (400 kHz) / Fast-Plus (1 MHz) with clock stretching up to 2 ms. I3C Mode: Legacy I²C fallback; supports common command codes (CCC), in-band interrupts (IBI), and dynamic address assignment (DAA).
3.3 Bus Arbitration & Multi-Drop Support The driver implements a bus-holding circuit after a START condition to prevent floating SDA corruption. In multi-module setups (up to 8 DIMMs per channel), the driver forces a deterministic turn-off delay to avoid collisions during a repeated START. 4. Electrical Characteristics (Typical at 1.2V, 25°C) | Parameter | Min | Typ | Max | Unit | |--------------------------|-------|-----|---------|------| | Input low voltage (VIL) | -0.3 | – | 0.3×VDD | V | | Input high voltage (VIH) | 0.7×VDD | – | 3.6 | V | | Output low voltage (VOL@4mA) | – | 0.15| 0.25 | V | | Slew rate (rising edge, open-drain) | – | 45 | 120 | ns | | Standby current | – | 2 | 5 | µA | | Propagation delay (SCL → SDA) | – | 35 | 70 | ns | 5. Application Circuit & PCB Layout Guidelines 5.1 Recommended External Components
Pull-up resistors on SCL and SDA (to VIO): 1.2 kΩ – 2.2 kΩ (I²C), 470 Ω (I3C). Decoupling: 0.1 µF + 4.7 µF per channel near VDD pin. Optional series termination: 22 Ω – 33 Ω on SDA_OUT for long backplanes. Technical Write-Up: CM2 SPD Driver 1
5.2 Layout Rules
Run SCL and SDA traces with ground shielding (coplanar GND on 4-layer board). Keep total stub length from driver to each SPD slave ≤ 15 mm. Avoid vias between driver and first SPD device. Place the driver physically closest to the host ASIC/PMIC to minimize host-side crosstalk.