Xilinx University Program - Dsp For Fpga Primer... Official

The XUP DSP for FPGA Primer is usually broken into distinct modules. Let’s walk through the typical syllabus.

A typical 32-tap FIR filter on a 200 MHz ARM Cortex-M takes ~32 cycles per sample. On an FPGA using the XUP primer’s systolic architecture, it takes 1 clock cycle for all 32 taps. That’s a 32x speedup—without increasing clock frequency. Xilinx University Program - DSP for FPGA Primer...